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Recognize some Amd64 instruction patterns
* mps/code/prmci6.c (IsSimpleMov): Actually do something. (IsRexPrefix, DecodeSimpleMov, RexR, RexB, RexX, DecodeDisp32) (SignedInsElt, RegValue, DecodeModRM, DecodeSIB, DecodeCB): New helpers. * mps/code/prmctest.c: New file. * mps/code/comm.gmk: Add prmctest. * mps/tool/testcases.txt: Here too.
This commit is contained in:
Helmut Eller
parent
51e1001a70
commit
698a403d32
4 changed files with 464 additions and 11 deletions
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@ -297,6 +297,7 @@ TEST_TARGETS=\
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mv2test$(EXEEXT) \
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nailboardtest$(EXEEXT) \
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poolncv$(EXEEXT) \
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prmctest$(EXEEXT) \
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qs$(EXEEXT) \
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sacss$(EXEEXT) \
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segsmss$(EXEEXT) \
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@ -568,6 +569,9 @@ $(PFM)/$(VARIETY)/nailboardtest$(EXEEXT): $(PFM)/$(VARIETY)/nailboardtest.o \
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$(PFM)/$(VARIETY)/poolncv$(EXEEXT): $(PFM)/$(VARIETY)/poolncv.o \
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$(POOLNOBJ) $(TESTLIBOBJ) $(PFM)/$(VARIETY)/mps.a
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$(PFM)/$(VARIETY)/prmctest$(EXEEXT): $(PFM)/$(VARIETY)/prmctest.o \
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$(TESTLIBOBJ) $(PFM)/$(VARIETY)/mps.a
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$(PFM)/$(VARIETY)/qs$(EXEEXT): $(PFM)/$(VARIETY)/qs.o \
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$(TESTLIBOBJ) $(PFM)/$(VARIETY)/mps.a
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@ -34,25 +34,197 @@ SRCID(prmci6, "$Id$");
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#error "prmci6.c is specific to MPS_ARCH_I6"
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#endif
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/* DecodeCB -- Decode an Intel x86 control byte into Hi, Medium & Low
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fields */
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static Bool IsSimpleMov(Size *inslenReturn,
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MRef *srcReturn,
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MRef *destReturn,
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MutatorContext context)
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static void DecodeCB(size_t *hReturn, size_t *mReturn, size_t *lReturn,
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Byte op)
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{
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*lReturn = op & 7;
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*mReturn = (op >> 3) & 7;
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*hReturn = (op >> 6) & 3;
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}
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/* DecodeSIB -- Decode a Scale Index Base byte for an Intel x86
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instruction */
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static void DecodeSIB(size_t *sReturn, size_t *iReturn, size_t *bReturn,
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Byte op)
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{
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DecodeCB(sReturn, iReturn, bReturn, op);
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}
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/* DecodeModRM -- Decode a ModR/M byte for an Intel x86 instruction */
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static void DecodeModRM(size_t *modReturn, size_t *rReturn,
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size_t *mReturn, Byte op)
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{
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DecodeCB(modReturn, rReturn, mReturn, op);
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}
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/* RegValue -- Return the value of a machine register from a context */
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static Word RegValue(MutatorContext context, size_t regnum)
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{
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MRef addr;
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addr = Prmci6AddressHoldingReg(context, regnum);
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return *addr;
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}
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/* Return a byte element of an instruction vector as a
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* Word value, with sign extension
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*/
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static Word SignedInsElt(Byte insvec[], Count i)
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{
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signed char eltb;
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eltb = ((signed char *)insvec)[i];
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return (Word)eltb;
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}
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static signed DecodeDisp32(Byte *bytes)
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{
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unsigned r = 0;
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size_t i;
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for (i = 0; i < 4; i++) r |= bytes[i] << (i * 8);
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return r;
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}
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static Word RexR(Byte rex) { return (rex >> 2) & 1; }
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static Word RexB(Byte rex) { return (rex >> 0) & 1; }
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static Word RexX(Byte rex) { return (rex >> 1) & 1; }
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static Bool DecodeSimpleMov(size_t *regnumReturn, MRef *memReturn,
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Size *inslenReturn, MutatorContext context,
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Byte insvec[])
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{
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Byte rex = insvec[0];
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Byte modRM = insvec[2];
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Word base, disp = 0, scaled_index = 0;
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size_t mod, reg, rm;
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DecodeModRM(&mod, ®, &rm, modRM);
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switch (mod) {
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case 0:
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switch (rm) {
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default:
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*inslenReturn = 3;
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base = RegValue(context, rm | (RexB(rex) << 3));
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goto done;
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case 4:
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*inslenReturn = 4;
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goto decode_sib;
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case 5: {
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Word rip = (Word)insvec;
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*inslenReturn = 7;
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base = rip + *inslenReturn;
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disp = DecodeDisp32(insvec + 3);
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goto done;
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}
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}
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case 1:
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switch (rm) {
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default:
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*inslenReturn = 4;
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disp = SignedInsElt(insvec, 3);
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base = RegValue(context, rm | (RexB(rex) << 3));
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goto done;
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case 4:
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*inslenReturn = 5;
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disp = SignedInsElt(insvec, 4);
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goto decode_sib;
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}
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case 2:
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switch (rm) {
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default:
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*inslenReturn = 7;
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disp = DecodeDisp32(insvec + 3);
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base = RegValue(context, rm | (RexB(rex) << 3));
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goto done;
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case 4:
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*inslenReturn = 8;
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disp = DecodeDisp32(insvec + 4);
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goto decode_sib;
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}
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case 3:
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return FALSE;
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default:
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NOTREACHED;
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}
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NOTREACHED;
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decode_sib: {
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size_t s, i, b;
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DecodeSIB(&s, &i, &b, insvec[3]);
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base = RegValue(context, b | (RexB(rex) << 3));
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if (i == 4 && !RexX(rex))
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scaled_index = 0;
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else
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scaled_index = (RegValue(context, i | RexX(rex) << 3) << s);
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}
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done:
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*memReturn = (MRef)(base + disp + scaled_index);
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*regnumReturn = reg | (RexR(rex) << 3);
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return TRUE;
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}
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static Bool IsRexPrefix(Byte b) { return (b >> 4) == 0x4; }
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static Bool IsSimpleMov(Size *inslenReturn, MRef *srcReturn,
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MRef *destReturn, MutatorContext context)
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{
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Byte *insvec;
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size_t regnum;
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MRef mem;
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MRef faultmem;
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Prmci6DecodeFaultContext(&faultmem, &insvec, context);
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/* Unimplemented */
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UNUSED(inslenReturn);
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UNUSED(srcReturn);
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UNUSED(destReturn);
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if (IsRexPrefix(insvec[0])) {
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switch (insvec[1]) {
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case 0x8b: /* MOV r64, r/m64 */
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if (DecodeSimpleMov(®num, &mem, inslenReturn, context,
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insvec)) {
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AVER(faultmem == mem); /* Ensure computed address
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matches exception */
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*srcReturn = mem;
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*destReturn = Prmci6AddressHoldingReg(context, regnum);
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return TRUE;
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} else
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return FALSE;
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case 0x89: /* MOV r/m64, r64 */
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if (DecodeSimpleMov(®num, &mem, inslenReturn, context,
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insvec)) {
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AVER(faultmem == mem); /* Ensure computed address
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matches exception */
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*destReturn = mem;
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*srcReturn = Prmci6AddressHoldingReg(context, regnum);
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return TRUE;
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} else
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return FALSE;
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default:
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return FALSE;
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}
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}
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return FALSE;
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}
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Bool MutatorContextCanStepInstruction(MutatorContext context)
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{
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Size inslen;
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@ -62,7 +234,7 @@ Bool MutatorContextCanStepInstruction(MutatorContext context)
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AVERT(MutatorContext, context);
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/* .assume.null */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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if (IsSimpleMov(&inslen, &src, &dest, context)) {
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return TRUE;
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}
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@ -79,7 +251,7 @@ Res MutatorContextStepInstruction(MutatorContext context)
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AVERT(MutatorContext, context);
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/* .assume.null */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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if (IsSimpleMov(&inslen, &src, &dest, context)) {
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*dest = *src;
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Prmci6StepOverIns(context, inslen);
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return ResOK;
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276
mps/code/prmctest.c
Normal file
276
mps/code/prmctest.c
Normal file
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@ -0,0 +1,276 @@
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/* prmctest.c: TEST INSTRUCTION EMULATION
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*
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* $Id$
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* Copyright (c) 2001-2020 Ravenbrook Limited. See end of file for license.
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*/
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#include "prmc.h"
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#include "prmcix.h"
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#include "testlib.h"
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#include <stdio.h>
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#if defined MPS_PF_LII6GC && !defined CONFIG_PF_ANSI
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#include <assert.h>
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#include <stdlib.h>
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#include <string.h>
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#define VERBOSE 0
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#pragma GCC diagnostic ignored "-Wpedantic"
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static void **asmcode(int) __attribute__((optimize(0)));
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static void **asmcode(int f)
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{
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static void *labels[] = {&&start, &&end};
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if (f)
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return labels;
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start:
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__asm__(
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"mov (%rax),%rax\n"
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"mov (%rcx),%r15\n"
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"mov (%r12),%rdx\n"
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"mov (%r13),%r8\n"
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"mov mem(%rip),%r8\n"
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"mov 0x8(%r14),%rsi\n"
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"mov 0xabcdef(%rax),%rax\n"
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"mov 0x1(%r12),%r8\n"
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"mov (%rax,%rdx,8),%rsi\n"
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"mov (%r8,%r9,1),%r8\n"
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"mov (%r8,%r12,2),%r8\n"
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"mov 0x10(%rax,%rdx,8),%rsi\n"
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/* TODO: "movq (%rax),%xmm1\n */
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);
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end:
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goto start;
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}
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static mps_word_t mem[8];
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static void testMovRm64ToR64(MutatorContext ctx, size_t srcreg,
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size_t disp, size_t scale, size_t idxreg,
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size_t dstreg, size_t len)
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{
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mps_word_t *gregs = (void *)ctx->ucontext->uc_mcontext.gregs;
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siginfo_t *siginfo = ctx->info;
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size_t ip0 = gregs[REG_RIP];
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const size_t some_value = (size_t)rnd_addr();
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memset(gregs, 0, sizeof(ctx->ucontext->uc_mcontext.gregs));
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memset(mem, 0, sizeof(mem));
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gregs[REG_RIP] = ip0;
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if (scale) {
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assert(idxreg != srcreg);
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gregs[idxreg] = rnd();
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}
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if (srcreg != REG_RIP) {
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gregs[srcreg]
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= (size_t)((Byte *)mem - disp - gregs[idxreg] * scale);
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}
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siginfo->si_addr = mem;
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mem[0] = some_value;
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if (!(dstreg == srcreg || (scale && dstreg == idxreg)))
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assert(gregs[dstreg] == 0);
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assert(gregs[dstreg] != some_value);
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assert(MutatorContextCanStepInstruction(ctx));
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assert(MutatorContextStepInstruction(ctx) == MPS_RES_OK);
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assert(gregs[dstreg] == some_value);
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assert(mem[0] == some_value);
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assert(gregs[REG_RIP] - ip0 == len);
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}
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struct regname {
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size_t num;
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const char *name;
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};
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static struct regname const gprs[] = {
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{REG_R8, "%r8"}, {REG_R9, "%r9"}, {REG_R10, "%r10"},
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{REG_R11, "%r11"}, {REG_R12, "%r12"}, {REG_R13, "%r13"},
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{REG_R14, "%r14"}, {REG_R15, "%r15"}, {REG_RDI, "%rdi"},
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{REG_RSI, "%rsi"}, {REG_RBP, "%rbp"}, {REG_RBX, "%rbx"},
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{REG_RDX, "%rdx"}, {REG_RAX, "%rax"}, {REG_RCX, "%rcx"},
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{REG_RSP, "%rsp"}, {REG_RIP, "%rip"},
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};
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static const char *regname(size_t regnum)
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{
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size_t i;
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for (i = 0; i < NELEMS(gprs); i++)
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if (gprs[i].num == regnum)
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return gprs[i].name;
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assert(0);
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}
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static char *open_tmpfile(const char *mode, FILE **f)
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{
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static const char *template = "/tmp/prmc-XXXXXX";
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char buf[32];
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int fd;
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strcpy(buf, template);
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fd = mkstemp(buf);
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assert(fd != -1);
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*f = fdopen(fd, mode);
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assert(*f != NULL);
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return strdup(buf);
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}
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static Byte *genCode(const char *txt, size_t *len)
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{
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FILE *a, *o, *s;
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char *aname = open_tmpfile("wb", &a);
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char *oname = open_tmpfile("rb", &o);
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char *sname = open_tmpfile("rb", &s);
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char cmd[256];
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size_t size, offset;
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Byte *code;
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if (VERBOSE)
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fprintf(stderr, "%s", txt);
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fprintf(a, "%s", txt);
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fflush(a);
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snprintf(cmd, sizeof cmd,
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"as %s -o %s"
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" && objdump -h %s "
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" | awk '/text/ "
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" { print $2 \" size: \" $3 \" offset: \" $6 }'"
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" >%s",
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aname, oname, oname, sname);
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assert(system(cmd) == 0);
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assert(fscanf(s, ".text size: %lx offset: %lx\n", &size, &offset)
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== 2);
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assert(fseek(o, offset, SEEK_SET) == 0);
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code = malloc(size);
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assert(code);
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assert(fread(code, 1, size, o) == size);
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remove(aname);
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remove(oname);
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remove(sname);
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free(aname);
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free(oname);
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free(sname);
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fclose(a);
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fclose(o);
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fclose(s);
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*len = size;
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return code;
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}
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static void genTest(MutatorContext ctx, size_t base, int32_t disp,
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size_t scale, size_t index, size_t dst)
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{
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char buf[1024];
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size_t len;
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Byte *code;
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if (scale)
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snprintf(buf, sizeof buf, "mov %d(%s,%s,%ld),%s\n", disp,
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regname(base), regname(index), scale, regname(dst));
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else
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snprintf(buf, sizeof buf, "mov %d(%s),%s\n", disp, regname(base),
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regname(dst));
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code = genCode(buf, &len);
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ctx->ucontext->uc_mcontext.gregs[REG_RIP] = (size_t)code;
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testMovRm64ToR64(ctx, base, disp, scale, index, dst, len);
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}
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static int32_t displacemts[] = {0, -1, 255, -256, 256, 0xabcdef01};
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static Bool filterRandomly(double probability)
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{
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return probability < rnd_double();
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}
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static void genTests(MutatorContext ctx)
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{
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const size_t NSCALEBITS = 3;
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const size_t NTESTS = NELEMS(gprs) * (NSCALEBITS + 1) * NELEMS(gprs)
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* NELEMS(gprs) * NELEMS(displacemts);
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const double probability = (double)500 / NTESTS;
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size_t b, sbits, i, d, e;
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for (b = 0; b < NELEMS(gprs); b++)
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for (sbits = 0; sbits < NSCALEBITS + 1; sbits++)
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for (i = 0; i < NELEMS(gprs); i++)
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for (d = 0; d < NELEMS(gprs); d++) {
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for (e = 0; e < NELEMS(displacemts); e++) {
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size_t base = gprs[b].num;
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size_t index = gprs[i].num;
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size_t dst = gprs[d].num;
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int32_t disp = displacemts[e];
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size_t scale = sbits ? (1 << sbits) : 0;
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if (dst == REG_RIP || (!sbits && i)
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|| (sbits && base == index) || index == REG_RSP
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|| base == REG_RIP || index == REG_RIP
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|| filterRandomly(probability))
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continue;
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genTest(ctx, base, disp, scale, index, dst);
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}
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}
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}
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static void runTests(void)
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{
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siginfo_t siginfo;
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struct ucontext_t ucontext;
|
||||
struct MutatorContextStruct ctx;
|
||||
MutatorContextInitFault(&ctx, &siginfo, &ucontext);
|
||||
ucontext.uc_mcontext.gregs[REG_RIP] = (size_t)(asmcode(1)[0]);
|
||||
|
||||
testMovRm64ToR64(&ctx, REG_RAX, 0, 0, 0, REG_RAX, 3);
|
||||
testMovRm64ToR64(&ctx, REG_RCX, 0, 0, 0, REG_R15, 3);
|
||||
testMovRm64ToR64(&ctx, REG_R12, 0, 0, 0, REG_RDX, 4);
|
||||
testMovRm64ToR64(&ctx, REG_R13, 0, 0, 0, REG_R8, 4);
|
||||
testMovRm64ToR64(&ctx, REG_RIP, 8, 0, 0, REG_R8, 7);
|
||||
testMovRm64ToR64(&ctx, REG_R14, 8, 0, 0, REG_RSI, 4);
|
||||
testMovRm64ToR64(&ctx, REG_RAX, 0xabcdef, 0, 0, REG_RAX, 7);
|
||||
testMovRm64ToR64(&ctx, REG_R12, 0x1, 0, 0, REG_R8, 5);
|
||||
testMovRm64ToR64(&ctx, REG_RAX, 0, 8, REG_RDX, REG_RSI, 4);
|
||||
testMovRm64ToR64(&ctx, REG_R8, 0, 1, REG_R9, REG_R8, 4);
|
||||
testMovRm64ToR64(&ctx, REG_R8, 0, 2, REG_R12, REG_R8, 4);
|
||||
testMovRm64ToR64(&ctx, REG_RAX, 0x10, 8, REG_RDX, REG_RSI, 5);
|
||||
|
||||
genTests(&ctx);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
testlib_init(argc, argv);
|
||||
|
||||
#if defined MPS_PF_LII6GC && !defined CONFIG_PF_ANSI
|
||||
runTests();
|
||||
#endif
|
||||
|
||||
printf("%s: Conclusion: Failed to find any defects.\n", argv[0]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* C. COPYRIGHT AND LICENSE
|
||||
*
|
||||
* Copyright (C) 2001-2020 Ravenbrook Limited <https://www.ravenbrook.com/>.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
|
@ -35,6 +35,7 @@ mpsicv
|
|||
mv2test
|
||||
nailboardtest
|
||||
poolncv
|
||||
prmctest
|
||||
qs
|
||||
sacss
|
||||
segsmss
|
||||
|
|
|
|||
Loading…
Reference in a new issue