From acf221316157dfea96b1de2aa8ca9f0dd94d9953 Mon Sep 17 00:00:00 2001 From: Benson Chu Date: Fri, 25 Oct 2024 22:05:38 -0700 Subject: [PATCH] riscv target --- lisp/llvm-lib/llvm-shared.el | 2 +- lisp/llvm-lib/my-clang-options.el | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lisp/llvm-lib/llvm-shared.el b/lisp/llvm-lib/llvm-shared.el index a396e42..76a187f 100644 --- a/lisp/llvm-lib/llvm-shared.el +++ b/lisp/llvm-lib/llvm-shared.el @@ -296,7 +296,7 @@ :tramp tramp-conn :root-dir root-dir :build-dirs-fun (lls/guess-build-dirs-fun root-dir) - :target (completing-read "Which target? " '("X86" "ARM" "Hexagon" "AIE")) + :target (completing-read "Which target? " '("X86" "ARM" "Hexagon" "AIE" "RISCV")) :bin-dirs-fun (lambda () (list (--> "/usr/bin/" diff --git a/lisp/llvm-lib/my-clang-options.el b/lisp/llvm-lib/my-clang-options.el index cf04d01..4626eb8 100644 --- a/lisp/llvm-lib/my-clang-options.el +++ b/lisp/llvm-lib/my-clang-options.el @@ -43,11 +43,11 @@ (register-prebaked-optionset clang-subtargets "ARM" cortex-m33 :target "-target arm -mcpu=cortex-m33 -mfpu=vfpv3-d16 -mfloat-abi=hard -mlittle-endian") -(register-prebaked-optionset clang-subtargets "riscv" rv32im +(register-prebaked-optionset clang-subtargets "RISCV" rv32im :target "-target riscv32-unknown-elf -march=rv32im -mabi=ilp32" :optimization "-O3") -(register-prebaked-optionset clang-subtargets "riscv" rv32imafc +(register-prebaked-optionset clang-subtargets "RISCV" rv32imafc :target "-target riscv32-unknown-elf -march=rv32imafc -mabi=ilp32f -mno-relax" :optimization "-O3")