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riscv target

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This commit is contained in:
Benson Chu 2024-10-25 22:05:38 -07:00
parent a39db49f68
commit acf2213161
2 changed files with 3 additions and 3 deletions
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2
lisp/llvm-lib/llvm-shared.el
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@ -296,7 +296,7 @@
:tramp tramp-conn
:root-dir root-dir
:build-dirs-fun (lls/guess-build-dirs-fun root-dir)
:target (completing-read "Which target? " '("X86" "ARM" "Hexagon" "AIE"))
:target (completing-read "Which target? " '("X86" "ARM" "Hexagon" "AIE" "RISCV"))
:bin-dirs-fun (lambda ()
(list
(--> "/usr/bin/"

4
lisp/llvm-lib/my-clang-options.el
View file

@ -43,11 +43,11 @@
(register-prebaked-optionset clang-subtargets "ARM" cortex-m33
:target "-target arm -mcpu=cortex-m33 -mfpu=vfpv3-d16 -mfloat-abi=hard -mlittle-endian")
(register-prebaked-optionset clang-subtargets "riscv" rv32im
(register-prebaked-optionset clang-subtargets "RISCV" rv32im
:target "-target riscv32-unknown-elf -march=rv32im -mabi=ilp32"
:optimization "-O3")
(register-prebaked-optionset clang-subtargets "riscv" rv32imafc
(register-prebaked-optionset clang-subtargets "RISCV" rv32imafc
:target "-target riscv32-unknown-elf -march=rv32imafc -mabi=ilp32f -mno-relax"
:optimization "-O3")